The model is verified by comparison to Monte-Carlo circuit simulations for 7-nm state-of-the-art FINFET technology. The developed model delivers easy means of evaluating delay variation of basic circuits. The standard deviation and mean of the circuit delay are expressed as functions of the standard deviation and mean of the effective and linear transistor currents. To analyze random variation, the effective current concept is employed wherein circuit delay is approximated by the product of the load capacitance and supply voltage over two times the effective current. In this article, analytical models for the within-die random variation of the inverter, nand and nor circuits are developed. Statistical circuit modeling becomes an important means of realizing such approaches.
The increase of within-die random variation accompanying continuing advancement of the semiconductor technology necessitates variation-aware approaches in circuit design and analysis. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. As a run-time technique, TED is the only method that accounts for both local and global variations. Each of these methods adds system complexity, area, and energy overhead. Typically, these techniques include replica paths, sensors, or TED. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques.
Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold.
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